ECE 3544:  Digital Design I

 

Instructor: Dr. Yang (Cindy) Yi
Office: 441 Whittemore Hall

Class Room and Time: Mon. and Weds. at 2:30 PM - 3:45 PM (Robeson Hall 105)

Email: cindy_yangyi@vt.edu

 

Teaching Assistant: Yu Guo

Office: 477 Whittemore Hall
Email: yug18@vt.edu

 


Schedule: 

Week of Topic Assignment
8/20/2018 Overview,
CMOS Digital circuits		 Ch. 1, 2.1-2.15.1 in 4th/5th Edition
Ch. 3 section 1-3 in 4th Edition         
Ch. 14 section 1 – 3, 4, 6.3 in 5th Edition
8/27/2018 Introduction to Hardware Descript Language,    
Verilog Structural Models		 Chapter 5 session 5.1, 5.4.1-5.4.4, 5.4.7 in 4th Edition
Chapter 5 session 5.1 –5.4, 5.7 in 5th Edition
HW1 (due on 09/05)
9/3/2018 Labor Day (No Class),
Combinational Logic Design-1		 Chapter 4 in 4th Edition
Chapter 3 in 5th Edition
9/10/2018 Combinational Logic Design-2          
Multilevel Circuits
Verilog Models, Modules, and Dataflow Models-1		 Chapter 5.4.2, 5.4.5, 5.4.8 in 4th Edition
Chapter 5.1, 5.2, 5.5, 5.8 in 5th Edition
Lab 1.a (due on 09/17)
HW2 (due on 09/24)
9/17/2018 Modules, and Dataflow Models-2                         
Chapter 5.4.2, 5.4.5, 5.4.8 in 4th Edition
Chapter 5.1, 5.2, 5.5, 5.8 in 5th Edition
Lab 1.b (due on 09/24)
9/24/2018 Procedural Models Chapter 5.4.9 in 4th Edition
Chapter 5.9 in 5th Edition
10/01/2018 Design Documentation
Combinational Logic Timing

Combinational Logic Function Blocks-1
Midterm Exam Coverage		 Chapter 6.1, 6.2 in 4th Edition
Chapter 4.1, 4.2 in 5th Edition
HW 3 (due on 10/08)
Chapter 6.4-6.8 in 4th Version
Chapter 6.3 – 6.4, 7.1 – 7.3 in 5th Version
Lab 2 (due on 10/18)
10/08/2018 Combinational Logic Function Blocks-2
Midterm Exam (10/10)		 Chapter 6.4-6.8 in 4th Version
Chapter 6.3 – 6.4, 7.1 – 7.3 in 5th Version
10/15/2018 Combinational Logic Function Blocks-3
Hardware Synthesis 		Chapter 5.4.15 in 4th Version
Chapter 5.15 in 5th Version
HW 4 (due on 10/25)
10/22/2018 Sequential Design Principles-1 Chapter 7 in 4th Version
Chapter 9, 10, 12.1 – 12.2 in 5th Version
Lab 3.a (due on 11/01)
10/29/2018 Sequential Design Principles-2
Sequential Design Practice		 Chapter 7 in 4th Version
Chapter 9, 10, 12.1 – 12.2 in 5th Version
Chapter 8.1-8.2, 8.4-8.5, 8.7-8.9 in 4th Version
Chapter 11, 13.1 in 5th Version
Final Project
11/5/2018 Timing Issues in Sequential Design Chapter 8.1-8.2, 8.4-8.5, 8.7-8.9 in 4th Version
Chapter 13.3 – 13.4 in 5th Version
Lab 3.b (due on 11/13)
11/12/2018 FSM Examples Chapter 7.7 in 4th Version
Chapter 12.3 – 12.9 in 5th Version
Lab 4 (due on 11/27)
HW 5 (due on 11/30)
11/19/2018 Thanksgiving Holidays
11/26/2018 Arithmetic Circuits Chapter 6.10 in 4th Version
Chapter 8.1 – 8.3 in 5th Version
12/03/2018 Final Exam Review  
12/05/2018 Final Project Presentation  
12/10/2018 10:05AM - 12:05PM Final Exam at our Classroom

 


© Copyright by Yang (Cindy) Yi.